In recent years, digital circuits have been developed to increase their speed. Chips operable at a high speed of at least 1 GHz have been in general use. With such high clock frequencies, the stability of clock signals is essential to the stability of the chip operation. It is difficult to transmit a high-speed clock of at least 1 GHz between chips. Therefore, there has generally been used a method of generating such a high-speed clock by a clock generator circuit provided on a chip. For this purpose, an oscillator circuit with stable operation should be mounted on a chip.
For oscillation of low frequencies, a ring oscillator has been used as an oscillator circuit formed on a chip. However, an oscillation frequency of a ring oscillator is determined by delay time of an inverter having a semiconductor circuit. Therefore, a ring oscillator is susceptible to temperature, voltage, noise, production variations, and the like, resulting in unstable operation.
LCVCO (LC Voltage-Controlled Oscillator) circuits, which employ resonance of an inductor (L) and a capacitor (C), are suitable to provide an oscillator circuit with higher accuracy than a ring oscillator. In order to implement an on-chip LCVCO circuit, an inductor and a capacitor need to be mounted on a chip. However, an inductance value of about a few nH is required to produce an oscillation frequency of about 1 GHz. Inductors with such an inductance value have a size of a few hundred μm square. Therefore, an inductor occupies a large area on a chip.
FIG. 1 is a block diagram of a general LCVCO circuit. In FIG. 1, the LCVCO circuit is formed by an inverter circuit and an oscillator circuit including an inductor and a capacitor. An oscillation frequency fo of this circuit is simply given by the following formula (1):
                    fo        ≈                  1                      2            ⁢            π            ⁢                          LC                                                          (        1        )            where L is an inductance value of the inductor, and C is a capacitance value of the capacitor.
A minimum requirement for this circuit to oscillate is that a gain along a loop shown by the arrow in FIG. 1 exceeds 1 at the oscillation frequency. However, a parasitic resistance or a parasitic capacitance of the inductor wiring cannot be ignored in the on-chip inductor. The parasitic capacitance can be regarded as part of the capacitance of the capacitor because of parallel connection to the capacitor connected in parallel to the inductor. However, because the series resistance decreases the gain, it is necessary to sufficiently reduce the series resistance.
FIGS. 2 and 3 show examples of an LCVCO circuit that implements the block diagram of FIG. 1. FIG. 2 shows an nMOS (negative channel Metal Oxide Semiconductor) circuit, and FIG. 3 shows a CMOS (Complementary MOS) circuit.
Referring to FIG. 2, an inverter circuit of the nMOS circuit is formed only by n-type MISFETs (Metal-Insulator-Semiconductor Field-Effect Transistors). Inductors are connected between each of drain terminals OUT3 and OUT4 of the two n-type MISFETs and a power source VDD. At the time of oscillation, voltages of OUT3 and OUT4 vary around a voltage of (the series resistance of VDD-inductors)×Ic/2 where Ic is a current flowing through the current source. In a general LCVCO, a series resistance of an inductor is as small as a few Ω. Therefore, the center voltage is almost the same as VDD.
Referring to FIG. 3, an inverter circuit of the CMOS circuit is formed by n-type MISFETs and p-type MISFETs. An inductor is connected between connection points OUT3 and OUT4 of drain terminals of the n-type MISFETs and the p-type MISFETs. Voltages of OUT1 and OUT2 are determined by balance of driving forces between the n-type MISFETs and the p-type MISFETs. Generally, the voltages of OUT1 and OUT2 are about a half of VDD.
FIG. 4 is a conceptual plan view of an LCVCO as an oscillator circuit using a conventional on-chip inductor. In FIG. 4, the inductor wiring uses the uppermost layer of wiring layers in a multilayer wiring structure. Furthermore, the capacitor uses a parasitic capacitance of the wiring or a gate capacitance of the MISFET in a case of a fixed capacitance and uses a gate capacitance of the MISFET or a junction capacitance of p+ and n+ of a silicon substrate in a case of a variable capacitance. In a multilayer metal wiring structure on a general silicon substrate, the film thickness of a wire in an upper layer is larger than that of a wire in a lower layer. Therefore, the uppermost layer wire, which has the largest film thickness, is used in order to reduce a series resistance of the wiring. Moreover, a wiring layer underneath the uppermost layer, which has a thickness smaller than the largest film thickness, may be used along with the uppermost layer wiring in order to reduce the series resistance. In this case, the wiring of the lower layer is not solely used and is connected in parallel or in series to the wiring of the uppermost layer. Furthermore, in a case of a wiring structure having a plurality of wiring layers with the largest film thickness, wires are connected in parallel or in series to the wiring of the uppermost layer. Additionally, in order to achieve a low series resistance, the total length of wiring is set to be about 1 mm, and the wire width is widened to be about 10 μm. In this case, for a general on-chip inductor having an inductance of about 1 nH, the series resistance is equal to or lower than 5Ω. However, an on-chip inductor uses a large chip area because wide wires are arranged over the total length of about 1 mm Furthermore, an MISFET used for an inverter circuit to operate this inductor has a large gate width in order to increase the gain. Generally, an MISFET having a gate width of about 100 μm is used.
Japanese laid-open patent publication No. 2005-341332 discloses an oscillator circuit having inverters, inductors, and capacitors for switching at a resonance frequency of the inductors and the capacitors. Furthermore, Japanese laid-open patent publication No. 06-061058 discloses an on-chip inductor device that is constructed three-dimensionally with a plurality of wiring layers. Additionally, Custom Integrated Circuit Conference, 2006, p. 671-674 discloses that a conventional LCVCO uses an inductance of about 1 nH to obtain an oscillation frequency of about 6 GHz.
Conventional on-chip inductors for an LCVCO, including the example shown in FIG. 4, require a large chip area in order to reduce a series resistance and maintain a sufficient inductance value. Accordingly, the area of the LCVCO also increases. Hence, the area of the chip semiconductor device also increases.